This is a divisional of U.S. patent application Ser. No. 10/874,995, filed Jun. 23, 2004 now U.S. Pat. No. 7,072,235, which is a continuation of U.S. patent application Ser. No. 10/233,871, filed Aug. 29, 2002 (now U.S. Pat. No. 6,757,202). Each of these prior applications are hereby incorporated by reference herein in their entireties.
This invention relates to bias sensing in DRAM (dynamic random access memory) sense amplifiers. More particularly, this invention relates to improving the refresh performance of DRAM devices.
As a result of charge leakage from DRAM memory cells, sense amplifier devices sense (or sample) and restore electrical charge within each of the memory cells of a given DRAM device. In order to sense and restore the electrical charge of a memory cell that is connected to a particular digit line, a sense amplifier compares the bias voltage on a “reference” digit line with the bias voltage on the digit line connected to the memory cell that is accessed (i.e., read).
If a logic “1” is stored in the accessed memory cell capacitor, upon accessing the memory cell, stored electrical charge from the capacitor is shared with the digit line. This slightly raises the voltage on the memory cell digit line relative to the reference digit line bias voltage. The sense amplifier detects this voltage change and applies a suitable voltage (e.g., Vcc) to the memory cell digit line such that the memory cell is recharged and restored to a full level of electrical charge.
If a logic “0” is stored in the memory cell capacitor, upon accessing the memory cell, the absence of stored electrical charge in the capacitor causes some electrical charge present on the biased digit line to be shared with the memory cell. This slightly reduces the voltage on the memory cell digit line relative to the biased reference digit line. The sense amplifier detects this voltage change and applies a ground (GND) signal to the memory cell digit line so that the accessed memory cell is fully discharged (i.e., logic “0”).
The refresh time or interval between sensing (i.e., reading) and restoring the electrical charge within memory cells is limited to the bias voltage level applied to the reference digit lines. For example, a DRAM memory cell holding an electrical charge representative of a logic “1,” is sensed after a finite time interval (refresh time). The sense amplifier then determines that a logic “1” is stored in the memory cell and restores its electrical charge to full value. However, if this refresh duration is too long, the electrical charge stored within this memory cell will degrade too much. When this occurs, the sense amplifier erroneously determines that a logic “0” is stored in the memory cell. Thus, it does not restore the memory cell electrical charge to its full value (i.e., logic “1”).
Therefore, for a memory cell storing a logic “1,” the refresh time must occur before the voltage on the sensed memory cell digit line drops below the reference digit line bias voltage. Otherwise, the DRAM device erroneously detects a logic “0.” To avoid this, the interval between refresh times must be reduced. However, by reducing the interval between refresh times, the power dissipation within the DRAM device undesirably increases. This becomes progressively problematic as DRAM memory arrays increase in memory capacity as their physical dimensions decrease. By reducing the reference digit line bias voltage, the time interval between the refresh operation (refresh time) increases as a result of providing an increased margin for electrical charge degradation in the memory cell.
It is known that by including dummy memory cells on the digit lines of DRAM memory devices, the bias voltage for any particular reference digit line can be reduced to improve the refresh performance. By reducing this bias voltage (threshold level), the probability of logic “1” detection increases (increasing reliability), and therefore, the required time between refresh operations increases.
However, the inclusion of dummy cells inefficiently uses fabrication area, which is particularly undesirable in light of the trend towards smaller DRAM array devices with increased memory capacity.
In view of the foregoing, it would be desirable to provide improved refresh performance in DRAM memory devices by varying the threshold or bias voltage used in the sensing operation.